1. Field of the Invention
The present invention relates to electrical circuits and, in particular, to a circuit that utilizes an asynchronous clock select input to control selection between two synchronous clock sources while eliminating spurious glitches on the clock output.
2. Discussion of the Prior Art
The clock supplied to a microprocessor must not exceed the maximum frequency requirement inherent in the microprocessor design. For a system where multiple frequency operation is desirable, it becomes necessary to provide a means for selecting the operating frequency. It is also desirable to be able to switch clock speed quickly without stopping the clock and, certainly, without "glitching" the clock, since this would be detrimental to the operation of the microprocessor.
Conventional clock select systems require stopping the clock altogether, selecting the new frequency, and then starting the clock up again at the new frequency. A system of this type is disclosed in U.S. Pat. No. 4,229,699, titled Multiple Clock Selection System, issued to Frissel on Oct. 21, 1980.
The system described by Frissel is adequate in applications where configuration time is not critical. However, in some applications, it is necessary to change speed "on the fly" to meet the requirements of the application. In both cases, it is essential that the selection process be glitch free, i.e. the transition from one clock frequency to another must be implemented in a manner such that small skews or spikes that could be interpreted as clock signals are avoided.